发明名称 |
Method and apparatus of clock control associated with read latency for a card device |
摘要 |
An SD memory card host controller supplies a clock to an SD memory card and issues a read command. After that, the host controller stops supplying the clock to the SD memory card during latency of read data from receipt of a response to the read command from the SD memory card to readout of data. The host controller resumes supplying the clock immediately before a data cycle starts. Power savings can thus be achieved by controlling the clock to be supplied to the SD memory card.
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申请公布号 |
US6990599(B2) |
申请公布日期 |
2006.01.24 |
申请号 |
US20020231245 |
申请日期 |
2002.08.30 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
TAKAMIYA TAKESHI;MAKI YASUNORI |
分类号 |
G06F1/04;G06K17/00;G06F1/32;G06F3/08;G06F12/00 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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