发明名称 PULL-DOWN DETECTION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To optimize the discrimination sensitivity of a video signal of a 24-frame source included in a 60-frame interlace signal. SOLUTION: The pull-down detection circuit detects a total time DT when 24-frame discrimination signals C outputted from a 24-frame discrimination circuit 10 are logical "1" for thirty seconds in the past (discrimination of 24-frame source), and a sensitivity reference value setting circuit 20 determines a sensitivity reference value REF of a comparator 13 in response to the time DT. When the time DT is greater, the REF is selected smaller and when the time DT is smaller, the REF is selected greater. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006020119(A) 申请公布日期 2006.01.19
申请号 JP20040196514 申请日期 2004.07.02
申请人 FUJITSU GENERAL LTD 发明人 ITO YASUSHI;MATSUNAGA SEIJI;ONODERA JUNICHI
分类号 H04N7/01 主分类号 H04N7/01
代理机构 代理人
主权项
地址