发明名称 Refresh-free dynamic semiconductor memory device
摘要 In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.
申请公布号 US2006013030(A1) 申请公布日期 2006.01.19
申请号 US20050165273 申请日期 2005.06.24
申请人 发明人 ARIMOTO KAZUTAMI;SHIMANO HIROKI;FUJINO TAKESHI;HASHIZUME TAKESHI
分类号 G11C5/06 主分类号 G11C5/06
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