TESTING A PIPELINE IN AN IC

摘要

An architecture for testing a pipeline (14) in an integrated circuit comprises an input port and an output port, and is operable to process a data word having a plurality of data bits. The architecture comprises a multiplexer (18) provided at each input of the input port of the pipeline (14), each multiplexer being operable to allow a data bit or test data bit to be input to the pipeline. A write test block (15) is operable to control the writing of data bits or test data bits to the pipeline (14) during a normal or test mode of operation, and a read test block (16) is operable to control the reading of data bits or test data bits from the pipeline during a normal or test mode of operation. The write test block (15) and the read test block (16) are operable in a test mode to control the pipeline (14) as a scan chain. The architecture requires less hardware and hence less silicon area than conventional test architectures.