| 摘要 |
<P>PROBLEM TO BE SOLVED: To receive parallel data while synchronizing phases between bits in a system for transmitting the parallel data at a high speed. <P>SOLUTION: A clock adjusting circuit 302 adjusts a clock signal clk on the basis of the changing point of a data signal it#0, and generates an adjusted clock signal iclk#0. A ring buffer 305 is configured by a plurality of buffer stages, and fetches the value of it#0 into a buffer indicated by the pointer of a write pointer circuit 304 in accordance with iclk#0. The pointer of a read pointer circuit 313 is updated according to a clock signal CLKIN, data of a buffer indicated by the pointer thereof are read out from each ring buffer 305 of bits #0-#(n-1) and are stored in a reception register 314. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
