发明名称 |
Methods of processing thick ILD layers using spray coating or lamination for C4 wafer level thick metal integrated flow |
摘要 |
A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The process flow may include forming an inter-layer dielectric with spray coating or lamination over a surface with high aspect ratio structures.
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申请公布号 |
US2006012039(A1) |
申请公布日期 |
2006.01.19 |
申请号 |
US20050221453 |
申请日期 |
2005.09.07 |
申请人 |
KIM SARAH E;LEE KEVIN J;TOWLE STEVEN;GEORGE ANNA M |
发明人 |
KIM SARAH E.;LEE KEVIN J.;TOWLE STEVEN;GEORGE ANNA M. |
分类号 |
H01L23/48;H01L21/3105;H01L21/44;H01L21/60;H01L21/768;H01L23/485;H01L23/522;H01L23/528;H01L23/532 |
主分类号 |
H01L23/48 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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