| 摘要 |
PROBLEM TO BE SOLVED: To provide a test bench capable of efficiently verifying a semiconductor integrated circuit and performing a test high in quality and diversity. SOLUTION: In the test bench having a bus model for verifying an ASIC, the bus model is provided with: an arbitration means for deciding which of a plurality of operating functions should be given priority based on an operation signal from the ASIC; an operating function selection means for selecting the operating function based on the priority information transmitted from the above adjustment means; a timing arbitration means for deciding the priority of the timing of the operation transaction; and a timing selection means for deciding the operation timing of the operating function based on the information transmitted from the timing arbitration means. COPYRIGHT: (C)2006,JPO&NCIPI
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