| 摘要 |
PROBLEM TO BE SOLVED: To provide a data transfer controller capable of arbitrarily changing priority order for performing data transfer without fixing it, in a state that the data transfer controller operates. SOLUTION: This data transfer controller has: input/output circuits 2, 3, 4 inputting/outputting data; DMA control circuits 18, 19, 20 controlling the transfer of the data inputted/outputted from the input/output circuits 2, 3, 4; a changeover circuit 11 changing over connection between the input/output circuits 2, 3, 4 and the DMA control circuits 18, 18, 20; and a competition control circuit 27 determining one DMA control circuit among the DMA control circuits simultaneously performing the transfer of the data on the basis of the predetermined priority order of the DMA control circuit when at least two of the DMA control circuits 18, 19, 20 perform the transfer of the data. The competition control circuit 27 transfers the data to the determined DMA control circuit. COPYRIGHT: (C)2006,JPO&NCIPI
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