发明名称 |
CACHE MEMORY SYSTEM AND METHOD CAPABLE OF ADAPTIVELY ACCOMMODATING VARIOUS MEMORY LINE SIZE |
摘要 |
PROBLEM TO BE SOLVED: To provide a cache memory system capable of adaptively being accommodated to sizes of various memory lines. SOLUTION: This cache memory system (25) comprises a cache memory (31) and cache logic (33). The cache memory has a plurality of sets of ways. The cache logic is configured to request a memory line in response to a cache mistake. The memory line represents a portion of a way line. The cache logic is configured to select one of the ways based on which portion of the way line is represented by the memory line. The cache logic is further configured to store the memory line in the selected way. COPYRIGHT: (C)2006,JPO&NCIPI
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申请公布号 |
JP2006018841(A) |
申请公布日期 |
2006.01.19 |
申请号 |
JP20050192415 |
申请日期 |
2005.06.30 |
申请人 |
HEWLETT-PACKARD DEVELOPMENT CO LP |
发明人 |
WALKER SHAWN;SOLTIS DONALD C JR;CARL P BURUMERU |
分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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