| 摘要 |
The invention is directed to a phase locked loop. The phase locked loop comprises a variable frequency divider for performing a fraction frequency division by switching a dividing value having an integer portion and a fraction portion; a memory for storing the fraction portion; and a data converter for adding the integer portion to the fraction portion from the memory based on a clock signal from the variable frequency divider to determine the dividing value to be supplied to the variable frequency divider.
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