摘要 |
<p>There is provided a FinFET having a low threshold value voltage formed at the upper corner of a semiconductor layer and suppressing a leak current attributed to a parasitic transistor. A manufacturing method of the FinFET is also provided. The field effect transistor includes a semiconductor region, a gate insulation film, a cap insulation film, a gate insulation film, a gate electrode arranged on the cap insulation film, and a source/drain region. A channel region is formed on the side surface of the semiconductor region. The field effect transistor is characterized in that at least a part of the side surface of the cap insulation film covered by the gate electrode in the side surface extension direction of the semiconductor region has a side surface-resistant etching region having an etching rate lower than SiO<sub</p> |
申请人 |
YAMAGAMI, SHIGEHARU;NEC CORPORATION;KOH, RISHO;TANAKA, KATSUHIKO;TAKEUCHI, KIYOSHI;WAKABAYASHI, HITOSHI;TERASHIMA, KOICHI;TAKEDA, KOICHI;NOMURA, MASAHIRO;TANAKA, MASAYASU |
发明人 |
KOH, RISHO;YAMAGAMI, SHIGEHARU;TANAKA, KATSUHIKO;TAKEUCHI, KIYOSHI;WAKABAYASHI, HITOSHI;TERASHIMA, KOICHI;TAKEDA, KOICHI;NOMURA, MASAHIRO;TANAKA, MASAYASU |