发明名称 METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGNING DEVICE AND LOGICAL DESIGN PROGRAM
摘要 PROBLEM TO BE SOLVED: To provide a method for designing a semiconductor integrated circuit, for suitably suppressing the generation of reinstatement after layout design. SOLUTION: In this method for designing an LSI including a logical design process (steps 110 to 130) and a physical design process (step 200), whether or not data (F1) prepared by the logical design process (steps 110 to 130) are data which are appropriately for being used in the physical design process (step 200) is estimated prior to the start of the physical design process (step 200), and the estimation result is feeded back to the logical design process (steps 110 to 130), and reflected on data (F1) to be prepared by the logical design process (steps 110 to 130). COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006018434(A) 申请公布日期 2006.01.19
申请号 JP20040193822 申请日期 2004.06.30
申请人 FUJITSU LTD 发明人 TAKEUCHI KAZUTAKA
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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