发明名称 Delay calculation method capable of calculating delay time with small margin of error
摘要 A delay calculation method that is capable of calculating delay time with a small margin of error is provided for delay calculation in a logic circuit. The operating characteristics of transistor are expressed with a fixed resistance and a power supply voltage that changes with time. The power supply voltage is represented as a waveform which is a combination of two straight lines: the one indicating that the voltage, after a fixed delay of t 0 , increases to V 1 during Deltat 1 ; and the one indicating that the voltage increases from V 1 to E during Deltat 2 and thereafter remains at the fixed value of E. A difference in the shapes of input waveforms is adopted as a correction parameter to determine the values of Deltat 1 , V 1 , and Deltat 2.
申请公布号 US2006015278(A1) 申请公布日期 2006.01.19
申请号 US20050174542 申请日期 2005.07.06
申请人 RENESAS TECHNOLOGY CORP. 发明人 KOMODA MICHIO
分类号 G01R29/02 主分类号 G01R29/02
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