| 摘要 |
The present invention describes a new computer architecture. A digital processor comprises processing units which comprise decoders for decoding a first part of the N- bit data word into digital code with only one bit high. These bits are processed in arithmetic modules, which receive outputs from two processing units, and an activation signal produced by an instruction circuit. The instruction circuit receives knowledge on the data to be processed by reading the second part of the N-bit data words. This second part may be divided into several so-called DNA groups. The DNA group contain information on the type of symbols/values of the data to be processed. Using this knowledge on the data, very fast and simple parallel processing can be executed. |
