发明名称 |
SEMICONDUCTOR STORAGE DEVICE |
摘要 |
<p><P>PROBLEM TO BE SOLVED: To make high-speed read possible in a semiconductor storage device of virtual grounding wire memory array configuration by suppressing a leakage current through a memory cell adjoining to a read-out target memory cell. <P>SOLUTION: The semiconductor storage device is equipped with; a readout circuit 3 which detects size of a memory cell current which flows in a readout target memory cell by selecting a pair of selection bit lines each connecting to the source/drain the of read-out target memory cell and impressing a prescribed voltage between the bit lines concerned; and a counter potential generation circuit 4 which generates a counter potential Vn2 which changes in the same direction as the change of a middle node potential Vn1 according to the size of a memory cell current based on a middle node potential Vn1 of a middle node N1 on a current path which supplies a memory cell current in a readout circuit 3 which serves as the potential higher than any potential of a pair of selection bit lines, and whose fluctuation band is larger than that of the middle node potential Vn1. The counter potential Vn2 is supplied to non-selection bit line which adjoins high potential side of a pair of selected bit lines. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
申请公布号 |
JP2006018946(A) |
申请公布日期 |
2006.01.19 |
申请号 |
JP20040197007 |
申请日期 |
2004.07.02 |
申请人 |
SHARP CORP |
发明人 |
YAMAMOTO KAORU;ITO NOBUHIKO;YAMAUCHI YOSHIMITSU |
分类号 |
G11C16/02;G11C16/04;G11C16/06 |
主分类号 |
G11C16/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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