| 摘要 |
<p>A reconfigurable digital signal processing system comprises a serial to parallel converter comprising at least one delay block and at least one decimation block arranged to convert, in use, a first serial signal with a first sampling rate to a multiplicity of parallel subband signals with a second sampling rate, wherein the second sampling rate is less than or equal to the first sampling rate. Processing blocks are arranged, in use, to process the subband signals to produce processed signals. A configuration controller is arranged to modify, in use, the decimation factor of each decimation block and to load, in use, a configuration into the memory of a processing block. A parallel to serial converter comprising at least one expansion block, the parallel to serial converter arranged to recover from the processed signals, in use, a second serial signal with a sampling rate substantially equal to the first sampling rate. In use, in normal run-time operation the decimation factor of each decimation block is equal to the number of subband signals and when, in use, run-time reconfiguration is required the configuration controller is arranged to decrease the decimation factor so that the second sampling rate increases; load the configuration into the memory of a processing block; and increase the decimation factor to again be equal to the number of subband signals.</p> |
