| 摘要 |
A signal processing circuit such as an arithmetic circuit for performing arithmetic operations such as multiplication and/or addition/subtraction and a circuit having a voltage-controlled transconductance has a first MOSFET arrangement M1,M2,M3,M4 for performing an arithmetic operation for given first operands VIN, VC and, preferably, at least one other MOSFET M5 for performing substantially the same arithmetic operation for given second operands with the second operands being chosen to influence the output of the first MOSFET circuit by at least reducing, and preferably, eliminating, the presence of an undesirable component of the output of the first MOSFET circuit. |
