| 摘要 |
An active matrix array device has a plurality of matrix array elements (100), each of which have a first capacitive device (120) coupled to a charging conductor (32m) via a first switch (100) being responsive to an addressing conductor (22n). In addition, the matrix array elements (100) comprise a second capacitive device (130) coupled to the first capacitive device (120) via a second switch (112) being responsive to en enable signal provided via an enable conductor (42n). The second capacitive device (130) is coupled to the control terminal of a third switch (114), which is coupled between the first capacitive device (120) and a potential source like the charging conductor (32m). The second capacitive device (130) is used to sample the voltage across the first capacitive device (120), which enables the third switch (114) if of an appropriate value, thus providing a conductive path between the first capacitive device (120) and the potential source. This arrangement allows for a low-power data refresh mode of the matrix array elements (100) with polarity inversion in subsequent refresh cycles.
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