发明名称 |
Analog delay locked loop with tracking analog-digital converter |
摘要 |
An analog DLL device includes a delay model for modeling delay time for buffering the external clock signal; a phase comparator for comparing a phase of the reference clock signal with an phase of an outputted signal from the delay model; a charge pump for pumping charges; a loop filter for generating a reference voltage; a voltage control delay line and a tracking digital-analog converter which converts the reference voltage to a digital value; and stores the digital value for keeping the reference voltage safely.
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申请公布号 |
US6987409(B2) |
申请公布日期 |
2006.01.17 |
申请号 |
US20030749448 |
申请日期 |
2003.12.31 |
申请人 |
HYNIX SEMICONDUCTOR INC. |
发明人 |
KIM SE-JUN;HONG SANG-HOON;KO JAE-BUM |
分类号 |
G06F1/04;H03L7/06;G06F1/06;H03K5/13;H03L7/081;H03L7/089;H03L7/099;H03M1/48 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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