发明名称 |
Semiconductor memory having dummy regions in memory cell array |
摘要 |
A memory cell array is partitioned into a plurality of memory regions each of which includes a plurality of sense amplifiers and each of which is established as a unit of data input/output. Dummy regions each are formed between every two memory regions and include dummy bit lines that are set to a predetermined voltage at least during the operation of the memory cell array. Since the dummy bit lines are wired between the bit lines of the two adjacent memory regions, the voltage change in the bit lines in any of the memory regions can be prevented from affecting the bit lines in the other memory regions. As a result, malfunction of semiconductor memories can be prevented.
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申请公布号 |
US6987698(B2) |
申请公布日期 |
2006.01.17 |
申请号 |
US20020289314 |
申请日期 |
2002.11.07 |
申请人 |
FUJITSU LIMITED |
发明人 |
BANDO YOSHIHIDE;YAGISHITA YOSHIMASA |
分类号 |
G11C7/00;G11C11/401;G11C7/18;G11C7/22;G11C11/4076;G11C11/4097 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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