发明名称 FIFO MEMORY DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a FIFO memory device which allows a system in a data transmission side to confirm data in a desired place out of data of which the number of registered data has been confirmed, without enlarging a circuit scale or complicating processing. SOLUTION: The FIFO memory device is provided with; an n-stage shift register 2 (n is an integer equal to or larger than 2) for successively shifting data supplied from a system 100 in the data transmission side; a first selection means 5 to which outputs of the first to n-th stages of the shift register 2 are inputted; a counting means 3 which is counted up at each time of supply of a write enable signal from the system 100 and is counted down at each time of supply of a read enable signal from a system 200 in a data reception side; and a second selection means 4 to which outputs of the first to n-th stages of the shift register 2 are inputted and a count output of the counting means 3 is supplied as a control signal for selecting an output of a corresponding stage of the shift register 2. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006012246(A) 申请公布日期 2006.01.12
申请号 JP20040185329 申请日期 2004.06.23
申请人 SONY CORP 发明人 HASHIRANO KEIGO
分类号 G11C7/00 主分类号 G11C7/00
代理机构 代理人
主权项
地址