| 摘要 |
PROBLEM TO BE SOLVED: To provide a processor design technique for supporting a large and complicated processor with high clock speed. SOLUTION: A processor contains multiple levels of registers having different access latency. A relatively small set of registers is contained in a relatively faster high level register bank, and a large, more complete set of the registers is contained in a relatively slower lower level register bank. Physically, the high level register bank is placed closer to functional logic which receives inputs from the registers. Preferably, the low level bank includes a complete set of all processor registers, and the high level bank includes a small subset of the registers, duplicating information in the low level bank. The high level bank is preferably accessible in a single clock cycle. COPYRIGHT: (C)2006,JPO&NCIPI
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