发明名称 TIMING MODEL, AND LSI DESIGN METHOD USING IT
摘要 PROBLEM TO BE SOLVED: To provide a method for efficiently designing an LSI including a functional block by use of a timing model having two kinds of modes of ideal clock condition and propagation clock condition. SOLUTION: The LSI design method using a functional block containing a plurality of flip-flops comprises steps of preparing a timing model usable in a first mode and in a second mode; performing functional design of elementary function containing one or more function blocks; performing logic synthesis for the elementary function determined by the functional design by use of the timing model of the functional block in the first mode; performing first timing analysis for the logically synthesized elementary function by using the timing model in the first mode; performing layout based on the result of the logic synthesis and the first timing analysis; and performing a second timing analysis by using the timing model in the second mode after the layout. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006012008(A) 申请公布日期 2006.01.12
申请号 JP20040190990 申请日期 2004.06.29
申请人 OKI ELECTRIC IND CO LTD 发明人 GOKO HIRONORI
分类号 G06F17/50;G06F9/45;H01L21/82 主分类号 G06F17/50
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