发明名称 |
Address generation unit for a processor |
摘要 |
A processor includes a memory port for accessing a physical memory under control of an address. A processing unit executing instructions stored in the memory and/or operates on data stored in the memory. An address generation unit ("AGU") generates address for controlling access to the memory; the AGU being associated with a plurality of N registers enabling the AGU to generate the address under control of an address generation mechanism. A memory unit is operative to save/load k of the N registers, where 2<=k<=N, triggered by one operation. To this end, the memory unit includes a concatenator for concatenating the k registers to one memory word to be written to the memory through the memory port and a splitter for separating a word read from the memory through the memory port into the k registers.
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申请公布号 |
US2006010255(A1) |
申请公布日期 |
2006.01.12 |
申请号 |
US20040515462 |
申请日期 |
2004.11.22 |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS N.V. |
发明人 |
VAN BERKEL CORNELIS H.;MEUWISSEN PATRICK P.E. |
分类号 |
G06F3/00;G06F9/38;G06F9/312;G06F12/02;G06F12/06;G06F15/78;G06T1/60 |
主分类号 |
G06F3/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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