| 摘要 |
A memory array device has a plurality of gate structure lines, adjacently disposed over a substrate along a direction, wherein at least a portion of the gate structure lines have memory function. A plurality of first doped regions, in the substrate at a side of a first line of the gate structure lines. A plurality of second doped regions, in the substrate at a side of a last line of the gate structure lines. Wherein the first doped regions and the second doped regions respectively for a plurality of pairs of doped region with respect to a plurality of bit lines. In other words, the conventional source/drain regions for each memory cell are saved. Instead, the gate lines are adjacently disposed together.
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