FIELD PROGRAMMABLE GATE ARRAY (FPGA) BASED WAVE PIPELINED ARRAY MULTIPLIER (WPARAM)
摘要
<p>The invention provides an improved m x n wave pipelined array multiplier using an array of combinational logic blocks and a set of registers connected to each of combinational logic block.</p>
申请公布号
WO2006003667(A1)
申请公布日期
2006.01.12
申请号
WO2004IN00188
申请日期
2004.06.30
申请人
DEPARTMENT OF INFORMATION TECHNOLOGY;LAKSHMINARAYANAN, GOPALAKRISHNAN;VENKATARAMANI, BALASUBRAMANIAN
