| 摘要 |
<P>PROBLEM TO BE SOLVED: To effectively reduce an interference noise generated between adjacent bit lines in one cross (open bit line type) dynamic RAM. <P>SOLUTION: Sub-arrays 8, 8 are arranged at the right and left sides of a row of sense amplifiers 7 as a center. Each sub-array has a number of dynamic memory cells MC.... A pair of complementary bit lines is composed of bit lines (BL0, NBL0) to (BLn, NBLn) in the same row at the sub-arrays 8, 8 positioned at the left and right sides of the row of sense amplifiers 7 to become an open bit line type. A first wiring pattern SLD formed in parallel with these bit lines and in the same wiring layer is arranged between the bit lines BL0 to BLn, NBL0 to NBLn in the sub-arrays 8, 8. These wiring patterns SLD are all set at fixed potential, such as power source potential. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
