| 摘要 |
PROBLEM TO BE SOLVED: To control the threshold voltage of a semiconductor device having a high dielectric constant gate insulation film with high precision. SOLUTION: A p-type well 3 is formed on the upper layer of a silicon substrate 1. Pole surface layer of the p-type well 3 is implanted with arsenic ions 4 and heat treated to form a p-type lightly doped layer 5. An HfAlOx film 7 and a polysilicon film 8 are then deposited on the substrate 1. Subsequently, the polysilicon film 8 is patterned to form a gate electrode 8a. After an n-type extension region 10a is formed by implanting arsenic ions 10 using the gate electrode 8a as a mask, a sidewall 13 is formed on the gate electrode 8a. Finally, an n-type source-drain region 15a is formed by implanting arsenic ions 14 using the sidewall 13 and the gate electrode 8a as a mask. COPYRIGHT: (C)2006,JPO&NCIPI
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