Semiconductor dynamic random access memory device comprises power lines formed on respective metal layers arranged at row and column decoders, having different widths

摘要

The device has power lines (P1,P2) formed on respective metal layers arranged at row decoder and column decoder, for supplying power to the memory array. The power line (P3) formed on the metal layer has larger width and the power line (P1) formed on the metal layer has smaller width. Signal lines (GIO,LIO) are routed such that the signal lines are isolated more broadly. An independent claim is also included for power and signal line routing method on the dynamic random access memory (DRAM) array.