| 摘要 |
PROBLEM TO BE SOLVED: To provide a circuit and a method for memory testing capable of shortening a memory testing time. SOLUTION: This circuit is provided with a data generator 10 for generating expectation value data, capture registers 22a to 22c connected to read data from a plurality of memories 21a to 21c and to transfer the data in parallel, comparator circuits 23a to 23c for comparing outputs of the plurality of capture registers with the expectation value data for each of the plurality of capture registers, an identification circuit 25 for identifying a comparator circuit which detects noncoincidence among the plurality of comparator circuits, a reading register 26 for storing memory read data from the memory detected for noncoincidence and memory identification information for identifying the memory, and an output register 12 for serially reading the memory read data of the detected noncoincidence and the memory identification information, and serially outputting data corresponding to the access information of the memory of the detected noncoincidence. COPYRIGHT: (C)2006,JPO&NCIPI
|
