Semiconductor integrated circuit design method, design support system for the same, and delay library

摘要

In a semiconductor integrated circuit design method for simulating a delay of a logic circuit based on delay values which are calculated for each kind of a plurality of cells composing the logic circuit or for each signal path of the logic circuit and which are stored in a delay library, the simulation is performed to a block including at least one cell, and a delay value varying dependent on a layout direction of the cell included in the block is used as the delay value in the delay library. By this method, timing verification can be performed according to the layout direction of each cell layouted on a wafer, attaining precise margin of the design and improving yield of the semiconductor integrated circuit.