发明名称 TEST POINT SETTING SYSTEM FOR SUBSTRATE EMBEDDED COMPONENT
摘要 PROBLEM TO BE SOLVED: To provide a test point setting system for setting test points necessary for embedded components without omission when there is any embedded component at the time of designing a multi-layer printed board. SOLUTION: This test point setting system comprises a step 1a for performing the preparation processing of an embedded component terminal table by extracting all the connecting terminals of components in which the arrangement faces of constituents configuring a multi-layer printed board are formed as inner layers by referring to a preliminarily prepared data file as for all the constituents, a step 1b for selecting the connecting terminal names being the first constituent from the prepared embedded component terminal table, a step 1c for performing test point retrieval processing to the selected connecting terminal names, a step 1d for deciding whether or not the test point setting is possible from the result of retrieval processing and a step for performing test point setting processing 1e when it is decided that the test point setting is possible, and for outputting the set test points as a test point list. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006011507(A) 申请公布日期 2006.01.12
申请号 JP20040183318 申请日期 2004.06.22
申请人 NEC TOPPAN CIRCUIT SOLUTIONS INC 发明人 TOYODA HIROTAKA;TANIDO ARATA
分类号 G06F17/50;G01R31/28;H05K3/00 主分类号 G06F17/50
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