发明名称 Modular-multiplication computing unit and information processing unit
摘要 The bit strings of multipliers B and N are converted through the use of the Booth's algorithm in units composed of a predetermined number of bits and the operation of AxB+uxN is executed by a carry save adder using the value of an integral multiple of multiplicand A corresponding to the multiplication result of the values of the converted multiplier B and multiplicand A and also the value of an integral multiple of multiplicand u corresponding to the multiplication result of the values of the converted multiplier N and multiplicand u. The operation result of AxB+uxN supplied from the carry save adder are added to the operation result in the past of AxB+uxN through the use of an adder and the added result is supplied as the result of a modular-multiplication operation S=S+AxB+uxN.
申请公布号 US2006008080(A1) 申请公布日期 2006.01.12
申请号 US20050176209 申请日期 2005.07.08
申请人 WASEDA UNIVERSITY 发明人 HIGASHI KUNIHIKO;HISAKADO TORU;GOTO SATOSHI;IKENAGA TAKESHI
分类号 H04K1/00 主分类号 H04K1/00
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