| 摘要 |
The carrier tape comprises a dielectric layer (12) with a backside (14) and a front side (18), adapted to support a chip (16) at a chip location on the back side, and a conductive layer (20), arranged on the front side of the dielectric layer as a leadframe patterned with contact pads (22) to be connected to respective terminals of the chip. The carrier tape further comprises an additional, perforated layer (30), arranged on the backside (14) of the dielectric layer, said additional layer being perforated so as to define a peripheral wall surrounding a clearance area (32) around the chip location. The peripheral wall provided by the perforated layer thereby forms a containment barrier against the flow of a coating resin (28) dispensed over the chip in the clearance area. |
