发明名称 |
Conditional execution of coprocessor instruction based on main processor arithmetic flags |
摘要 |
A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type.
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申请公布号 |
US6986023(B2) |
申请公布日期 |
2006.01.10 |
申请号 |
US20020215756 |
申请日期 |
2002.08.09 |
申请人 |
INTEL CORPORATION |
发明人 |
PAVER NIGEL C.;MAGHIELSE WILLIAM T.;YU WING K.;LIU JIANWEI;JEBSON ANTHONY;BAVARIA KAILESH B.;PARIKH RUPAL M.;DENG DELI;PATEL MUKESH;FULLERTON MARK;GANESHAN MURLI;STRAZDUS STEPHEN J. |
分类号 |
G06F15/16;G06F9/00;G06F9/30;G06F9/302;G06F9/38;G06F15/00 |
主分类号 |
G06F15/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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