| 摘要 |
PROBLEM TO BE SOLVED: To reduce the number of times of timing ECO (Engineering Change Order) by arranging an inserting cell and a moving cell optimally on an already arranged wiring. SOLUTION: The timing regulation is achieved by a timing regulating method in the layout processing of a semiconductor integrated circuit wherein a computer is provided with a net defining procedure, a number of hypothesis point operating procedure, and an arrangement position determining procedure. In this case, the net defining procedure defines a region from at least one or more of fore stage cell at the output side of an objective cell to the rear stage cell at the input side of the objective cell on an already arranged wiring which is an objective to avoid a timing error as one set of net. The hypothesis point number operating procedure operates a number, more than the number of objective cells in one net, as the number of hypothesis points which become a hypothesis for arranging the objective cell. The arrangement position determining procedure arranges a plurality of hypothesis points on the already arranged wiring, and determines a hypothesis point having the value of timing error nearest to zero among the plurality of hypothesis points as the arranging position of the objective cell. COPYRIGHT: (C)2006,JPO&NCIPI
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