发明名称 Ratioed logic circuits with contention interrupt
摘要 A ratioed logic gate includes a contention interrupt circuit. The ratioed logic gate includes a pull up network coupled to a pull down network. Multiple inputs are coupled to turn the pull down and pull up networks on and off. An output is coupled to apply a logical function on the multiple inputs. A contention interrupt circuit is coupled to one of the pull up and the pull down networks to open circuit the one of the pull up and pull down networks when the pull up and pull down networks are in contention.
申请公布号 US2006001452(A1) 申请公布日期 2006.01.05
申请号 US20040881891 申请日期 2004.06.30
申请人 WIJERATNE SAPUMAL;DELEGANES DANIEL J 发明人 WIJERATNE SAPUMAL;DELEGANES DANIEL J.
分类号 H03K19/094 主分类号 H03K19/094
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