| 摘要 |
A power-saving multi-bit delta-sigma-converter (1) has an input (2) for analog signal (ZA) and an output for a digital output signal (ZD), a D/A converter (4), a summation device (5) for providing the difference between the input signal and the feedback signal (Z3), a filter (6) for the difference signal (Z1), a clocked quantization device (7) for quantizing the filtered difference signal (Z2) to the digital output signal (ZD) with bit-width N. The quantization device (7) has less than (2 power N)-1 comparators which compare the filtered signal (Z2) with a reference potential associated with each one of the comparators, and output the result at a decoder.
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