| 摘要 |
The present invention facilitates semiconductor fabrication by maintaining uniform thickness of a gate oxide layer ( 112 ) during the oxide growth process of non-volatile memory devices ( 100 ). The uniform thickness of a gate oxide layer ( 112 ) is obtained by defining the boundaries of the source and drain areas ( 110 ) of a memory device ( 100 ) with the source/drain dopant masking and implanting operation. If an isolation barrier ( 108 ) is present it is kept a minimum safe distance ( 130 ) away from the periphery of the conductive gate layer ( 114 ) to avoid birds-beak regions ( 30 ) responsible for non-uniform gate oxide growth. As a result, the corresponding charge losses and weak cells are mitigated, thereby facilitating the fabrication of more reliable memory cells ( 100 ). Because a more uniform gate oxide thickness ( 112 ) is used in association with the memory cells ( 100 ), a single significantly thinner gate oxide layer ( 114 ) may be employed throughout the memory device ( 100 ). In this way, the same gate oxide layer ( 114 ) may be used by an NVM device ( 100 ) embedded with common CMOS devices to reduce wafer manufacturing costs.
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