发明名称 |
MEMORY DEVICE WITH A DATA HOLD LATCH |
摘要 |
<p>A memory device includes a plurality of pairs of complimentary bit lines (200, 202) and a plurality of latch circuits. Each pair of the plurality of pairs of complimentary bit lines is coupled to a column of memory cells (31, 37). Each latch circuit has an input coupled to a data line and a first output and a second output to provide complementary latched values dependent upon a value of the data line. For each latch of the plurality of latches, the first output is coupled to a first bit line of a pair of the plurality such that a value of the first bit line is continuously determined by the first output during memory device operation and the second output is coupled to a second bit line of the pair such that a value of the second bit line is continuously determined by the second output during memory device operation.</p> |
申请公布号 |
WO2006001910(A2) |
申请公布日期 |
2006.01.05 |
申请号 |
WO2005US15858 |
申请日期 |
2005.05.05 |
申请人 |
FREESCALE SEMICONDUCTOR, INC.;RAMARAJU, RAVINDRARAJ;HOEKSTRA, GEORGE P.;KENKARE, PRASHANT U. |
发明人 |
RAMARAJU, RAVINDRARAJ;HOEKSTRA, GEORGE P.;KENKARE, PRASHANT U. |
分类号 |
E06C7/10;G11C7/00;G11C7/10 |
主分类号 |
E06C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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