| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock filter circuit which can obtain a clock signal filtering off an unnecessary high frequency signal which has little phase delay to an input signal. <P>SOLUTION: The clock filter circuit includes a transistor 100 having drains connected through a resistive element 102 between them, inputting an input clock signal CLK1 to a gate and a source connected to a VDD, a transistor 102 having a source grounded, a capacitor 103 connected to the drain of the transistor 102 and the ground, a delay circuit 2 having a CMOS inverter 104 connected to the drain of the transistor 100, a delay circuit 3 to which the inversion of the signal CLK1 is inputted instead of the clock CLK1 in the same constitution as the delay circuit 2, an AND circuit 4 inputting the inversion of the signal CLK1 and the output of the delay circuit 2, an AND circuit 5 inputting the input clock signal CLK1 and the output of the delay circuit 3, and an RS type flip-flop having the output of the AND circuit 4 as a RESET and the output of the AND circuit 5 as a SET. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
