发明名称 ASHING METHOD
摘要 PROBLEM TO BE SOLVED: To provide an ashing method capable of suppressing the occurrence of resist remainder after ashing. SOLUTION: In an ashing apparatus in which a chamber is commonly used for a reaction chamber and a vacuum discharge chamber, a semiconductor 112 is kept at a position spaced from a sample table 113 kept at a high temperature of 200°C or more until the reaction chamber becomes a vacuum state, the semiconductor substrate 112 is set on the sample table 113 to increase the temperature of it at a state in which the reaction chamber becomes the vacuum state and oxygen plasma ashing is performed, thereby preventing the resist remainder. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006005181(A) 申请公布日期 2006.01.05
申请号 JP20040180362 申请日期 2004.06.18
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MAEDA KENICHI;HISAKURE SHIYUNSUKE
分类号 H01L21/3065;H01L21/304 主分类号 H01L21/3065
代理机构 代理人
主权项
地址