| 摘要 |
PROBLEM TO BE SOLVED: To provide a device for performing the self optimization of the adjustment of the self refresh cycle of a DRAM, according to the capability of the device, over a wide temperature compensation range. SOLUTION: The device is loaded with a BIST (built-in self test) circuit. There are provided an error rate measuring circuit for detecting the error rate (error count) by the refresh cycle, by performing the reading/writing for a monitor bit area for each refresh cycle and a control circuit for performing the control for extending or shortening the refresh cycle so that it is at a prescribed error rate. The BIST circuit is the circuit for issuing an internal command and an internal address and for internally operating the DRAM, and performs the writing/readout of desired data, expectation comparison (error determination), and the error count. COPYRIGHT: (C)2006,JPO&NCIPI
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