REDUNDANT PROCESSING ARCHITECTURE FOR SINGLE FAULT TOLERANCE

摘要

An electronic module is provided. The module includes a first logic device having at least two processors and a first comparator and a second logic device having at least one prcessor and a second comparator. Each of the at least two processors are coupled to each of first and second comparators. The first and second comparators operate as a distributed comparator system. Each comparator independently identifies faults in the processors.