| 摘要 |
In a pulse width modulation circuit, a multiphase clock generation section generates a multiphase clock signal according to a reference clock. Then, a pulse width modulation signal is generated according to input data and the multiphase clock signal generated by the multiphase clock generation section. The multiphase clock generation section has a phase lock loop circuit and generates the multiphase clock signal by phase-interpolating an intermediate clock signal generated by the phase lock loop circuit.
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