| 摘要 |
There is provided a Clock recovery apparatus comprising: an early/late voter for deciding whether a current sampling point needs to be advanced or retarded, wherein said early/late voter passes an Up/Down signal to an interpolator for maintaining a clock signal; a frequency accumulator and rate multiplier 30 for generating further signals which are summed with those of the Up/Down signal of the early/late voter to provide an improved control signal to the phase interpolator. The accumulator is responsive to frequency changes in the input signal, and said interpolator acts on said Up/Down signals to adjust the clock signal by stepping it forward or backward according to control need, so that said sampling point can be advanced or retarded.
|
