| 摘要 |
It is intended to attain accurate parallel data transmission between a plurality of synchronous circuits operating at independent clocks, and to suppress increase of the scale of circuit at the minimum. A synchronous circuit controller comprises a delay section (3) for delaying data (D11) three times with a step with amount of delay (d1), and outputting corresponding delay data (D12-D14), a latch section (4) for latching each of the data (D11-D14) in synchronization with a clock (CK2), and outputting latch data (L11-L14), a comparator circuit (5) for comparing the latch data (L11-L14) each other in the ascending order of the amount of delay, detecting matching or non-matching between signals to be compared, and outputting comparison signals (C11-C13) corresponding to the detection results, respectively, and a selector circuit (6) for selecting one of the data (D11-D13) as synchronous data (DS) in response to control of the comparison signals (C11-C13). <IMAGE> |
