Method and system for correcting errors during read and write to non volatile memories

摘要

The invention relates to a method and system for correcting errors in multilevel memories, both of the NAND and of the NOR type. The method provides the use of a BCH correction code made parallel by means of a coding and decoding architecture allowing the latency limits of prior art sequential solutions to be overcome. Two possible solutions are shown. The parallelism being used for blocks C, 1 and 3 can be chosen in order to optimise the system performances in terms of latency and device area.