| 摘要 |
<p>A data reception apparatus adjusts a first clock signal to form an adjustment clock signal, and fetches the data signal in a data buffer (102), using a data signal in accordance with the adjustment clock signal in such a way that a set-up time and a hold time of the data signal are secured for each bit or for each group of parallel data. Then, a read device (103) selects the data of a plurality of bits in the data buffer in chronological order and reads out the selected data as parallel data, in accordance with a second clock signal. The data reception apparatus ensures that data can be received in parallel at high speed whilst retaining synchronism between bits.</p> |
