| 摘要 |
Gate and source electrodes (106,108) are connected to intersecting gate and data lines (102,104), respectively. A passivation layer is formed on a semiconductor layer that forms a channel between the source electrode and drain electrode (110). A gate pad (150) has a lower electrode (152) that extends from the gate line, while a data pad (160) has a bottom electrode (162) that separates from the data line. An independent claim is also included for a thin film transistor (TFT) array substrate manufacturing method. |
